1. Field of the Invention
The invention relates to a semiconductor device having, for example, a MOS (Metal Oxide Semiconductor) type capacitor and a manufacturing method thereof.
2. Related Art
With recent improvement in integration and functionality of semiconductor integrated circuit devices, higher capacitance and lower leakage current characteristics have been required for MOS type capacitor elements (MOS type capacitors). However, it is difficult to satisfy these two characteristics with the same MOS type capacitor. Therefore, it has been considered to form a capacitor having a high capacitance value (high capacitance capacitor) and a capacitor having a low leakage current value (low leakage current capacitor) depending on the applications in order to implement a MOS type capacitor satisfying the two characteristics. A typical method for forming these two kinds of capacitors is to form a thin insulating film for a high capacitance capacitor and a thick insulating film for a low leakage current capacitor. Hereinafter, a method for manufacturing such a conventional MOS type capacitor will be described with reference to the figures. FIGS. 9A through 9J are cross-sectional views illustrating the method for manufacturing the conventional MOS type capacitors. Note that, as shown in FIG. 9A, a semiconductor substrate 101 has a first region 102 where a low leakage current capacitor is to be formed, and a second region 103 where a high capacitance capacitor is to be formed.
As shown in FIG. 9B, an insulating film 104 is formed on the semiconductor substrate 101 by oxidation or the like. As shown in FIG. 9C, a resist pattern 105 is formed on the insulating film 104 in the first region 102, and then the insulating film 104 in the second region 103 is selectively removed.
As shown in FIG. 9D, after the resist pattern 105 is removed, a first insulating film 106 is formed on the semiconductor substrate of the first region 102 by, for example, oxidizing the insulating film 104 and a second insulating film 107 is formed on the semiconductor substrate of the second region 103. The thickness of the first insulating film 106 is larger than that of the second insulating film 107.
As shown in FIG. 9E, a silicon film 108, for example, is then formed over the whole surface of the semiconductor substrate 101. As shown in FIG. 9F, the silicon film 108, the first insulating film 106, and the second insulating film 107 are patterned by lithography and dry etching to form a first electrode 109 on the first insulating film 106 of the first region 102 and a second electrode 110 on the second insulating film 107 of the second region 103. A low leakage current MOS capacitor is thus formed in the first region 102 and a high capacitance MOS capacitor is formed in the second region 103.
As shown in FIG. 9G, impurities are implanted to the first electrode 109 and the second electrode 110 by ion implantation. At this time, impurities 111 are implanted also to a region located beside the first electrode 109 and the second electrode 110 in the semiconductor substrate 101 when viewed two-dimensionally. As a result, an impurity region 112 is formed. Note that, in a normal semiconductor device having a MOS type capacitor mounted thereon, not only a capacitor but elements such as a MOS transistor are formed simultaneously. Accordingly, for example, an extension region, an LDD (Lightly Doped Drain) region, and a pocket region of a transistor are formed simultaneously by this ion implantation.
As shown in FIG. 9H, after an insulating film is formed over the whole surface of the semiconductor substrate 101, the insulating film is selectively removed by dry etching to form a sidewall 113 on the respective side surfaces of the first electrode 109 and the first insulating film 106 and on the respective side surfaces of the second electrode 110 and the second insulating film 107. Note that, for example, a sidewall of a MOS transistor is formed simultaneously in this step.
As shown in FIG. 9I, ion implantation is performed in the first region 102 and the second region 103, whereby impurities 114 are further introduced into the first electrode 109 and the second electrode 110. At this time, impurities are also implanted to a region located beside the first electrode 109 and the second electrode 110 in the semiconductor substrate 101 when viewed two-dimensionally. As a result, a high concentration impurity region 115 is formed. For example, source/drain regions of a MOS transistor are formed simultaneously in this step.
As shown in FIG. 9J, the semiconductor substrate 101 is subjected to heat treatment such as RTA (Rapid Thermal Annealing) or LSA (Laser Spike Annealing) to activate the impurities implanted in each layer. The conventional MOS type capacitor having a low leakage current capacitor and a high capacitance capacitor in the first region 102 and the second region 103, respectively, can be manufactured by the above method.
Hereinafter, characteristics of a commonly used MOS type capacitor will be described with reference to FIGS. 10A through 10E. FIG. 10A is a cross-sectional view showing a structure of a commonly used MOS type capacitor.
As shown in FIG. 10A, a commonly used MOS type capacitor includes a semiconductor substrate 201, an insulating film 202 and an electrode 203 that are formed on the semiconductor substrate 201, a sidewall 205 formed on the respective side surfaces of the insulating film 202 and the electrode 203, and an impurity region 204 and a high concentration impurity region 206 that are formed in the semiconductor substrate 201. The impurity region 204 and the high concentration impurity region 206 are respectively formed beside the electrode 203 and the sidewall 205 when viewed two-dimensionally. When a voltage is applied to the MOS type capacitor, a depletion layer is formed in the semiconductor substrate 201 or the electrode 203. This changes the electrical thickness of the insulating film (electrical insulating film thickness) and thus changes the capacitance value and leakage current value of the capacitor.
FIG. 10B shows an impurity concentration distribution in the electrode 203. Note that FIG. 10B shows an impurity concentration in a region from the top surface to the bottom surface of the electrode 203 (between A and B). Impurities are introduced into the electrode 203 by ion implantation. Therefore, in the impurity distribution between A and B in the electrode 203, an impurity concentration reduces toward the bottom surface of the electrode 203, as shown in FIG. 10B.
FIG. 10C shows a leakage current value of the MOS type capacitor with respect to the electrical insulating film thickness (gate oxide film thickness). As shown in FIG. 10C, a leakage current reduces with increase in the electrical insulating film thickness. More specifically, as the thickness is increased by about 0.2 nm to about 0.3 nm, the leakage current value reduces by about one digit. It can be seen from FIG. 10C that the leakage current value significantly changes with a slight change in the film thickness.
FIG. 10D shows a capacitance value of the MOS type capacitor with respect to the electrical insulating film thickness (gate oxide film thickness). The capacitance value (C) of the capacitor is generally shown by C∝e×e0×S/d, where e is a relative dielectric constant, e0 is a dielectric constant, S is an area, and d is an insulating film thickness. This formula shows that the insulating film thickness (d) is inversely proportional to the capacitance value (C), and the capacitance value reduces with increase in the insulating film thickness.
As described above, the electrical insulating film thickness and the leakage current value and the capacitance value have the above relation. Therefore, as shown in FIG. 9J, a semiconductor device including a capacitor having a high capacitance value and a suppressed leakage current is conventionally implemented by forming insulating films having different thicknesses from each other on the same semiconductor substrate.
FIG. 10E shows a capacitance value with respect to the electrode area. It can be seen from the above formula of the capacitance value (C) and from FIG. 10E that the capacitance value is proportional to the area. Note that, in one proposed method, a high capacitance value is assured by forming a thick insulating film to suppress a leakage current and by increasing the electrode area in a high capacitance capacitor (see Japanese Laid-Open Patent Publication No. 2002-343879).
In another proposed method, after a MOS type capacitor is formed, an opening is formed in an interlayer insulating film formed in a formation region of a second MOS type capacitor, and an interlayer insulating film is formed again as an insulating film of the MOS type capacitor (see Japanese Laid-Open Patent Publication No. 2000-195966).